The present invention relates to methods for determining common mode voltages, particularly for use for discriminating data received by a memory device, such as a synchronous dynamic random access memory (SDRAM).
Double data rate physical layer designs employ a multi-drop bus for communication between a memory controller and a synchronous dynamic random access memory device. The multi-drop bus has a number of single-ended and unidirectional command lines and single-ended and bidirectional data lines. Each of the command and data lines is associated with an additional differential pair of clock lines to perform a source-synchronous operation.
The determination of the incoming data on a data line may be done in an evaluation unit of a receiver in the memory controller. To determine the logical level of the received single-ended data, the receiver comprises a comparator, which compares the received signal to a reference voltage. Ideally, the reference voltage is chosen equal to the common mode voltage of the received signal. Signal voltages higher than the common mode level are assigned to a logical “1”, those below are assigned to a logical “0”. In practice, an amplification or equalization stage is used in front of the comparator or data slicer. Analogously to the comparator the reference voltage at the input differential pair of the continuous-time linear equalizer (CTLE) is chosen equal to the common mode level of the received single-ended signal. The provision of a reference voltage that equals the common mode voltage for each of the single-ended data lines is therefore required in the memory controller.
An appropriate determination of the reference voltage is key to determining the eye opening in the evaluation unit of the memory controller. The closer the reference voltage is chosen to the actual common voltage of the data signal on the respective data line, the wider the eye opening of the received data gets.
Document US 2014/0119137 A1 discloses a computing system comprising a processor, a memory to be coupled to the processor and to interpret digital data, received over a memory bus, based on a reference voltage, and a voltage control circuit to dynamically adjust the reference voltage. The dynamical adjustment of the reference voltage is based on a statistical analysis (e.g. bit error rate measurements) and requires a sufficiently high statistical confidence level (e.g. 95%), which requires long measurements times.
In document “Setting Memory Device Vref In A Memory Controller and Memory Device Interface in a Communication Bus”, IP.COM Disclosure, No. IPCOM000196496D, Jun. 3, 2010 discloses a method for improving the AC performance characteristics of an interface by making adjustments to the Vhigh and Vlow reference levels that are detected by the receiving devices and ultimately matching them to the actual high and low values seen in system operation. This adjustment is normally accomplished during the time when the system is powered up and is performing driver training with deterministic data patterns. By matching the Vhigh and Vlow reference levels as sensed by the controller to a double data rate dynamic random access memory (DDR DRAM), a more accurate Vref for the DDR DRAM device will compensate for differences from the expected value due to variations in driver strength, termination strength, board resistor impedance variation, and other parasitic effects.